1. Field of the Invention
The present invention relates to a level shift circuit for converting a logic level, and more particularly relates to a circuit configuration for performing a low voltage operation with low power consumption.
2. Description of the Prior Art
As a known level shift circuit, for example, a latch type level shift circuit has been known. A level shift circuit of this type is shown in FIG. 1.
The level shift circuit of FIG. 1 includes two n-type transistors N51 and N52, cross-coupled two p-type transistors P51 and P52, and an inverter INV50. A gate of each of the p-type transistors P51 and P52 is connected to a drain of the other one of the p-type transistors P51 and P52. The inverter INV50 inverts an input signal IN and is operated by a low voltage supply VDD of, for example, 1.5 V or the like. Other devices than the inverter INV50 are devices at the high voltage side, which are operated by a high voltage supply VDD3 of, for example, 3.3 V or the like. The n-type transistors N51 and N52 have sources grounded and receive signals complementary to each other, i.e., an input signal IN and a reverse signal XIN of the input signal IN output from the inverter INV50, respectively. Each of the p-type transistors P51 and P52 has a source connected to the high voltage supply VDD3 and a gate connected in cross-coupling connection to a drain of the other one of the p-type transistors P51 and P52. Respective drains of the p-type transistors P51 and P52 are connected to respective drains of the n-type transistors N51 and N52, respectively. Assume that one connection point, i.e., a connection point of the p-type transistor P51 and the n-type transistor N51 is, a node W51 and the other connection point, i.e., a connection point of the p-type transistor P52 and the n-type transistor N52 is a node W52. An output signal OUT is output from the node W52.
The operation of the level shift circuit of FIG. 1 will be described. In a steady state, for example, when the input signal IN is at the H (VDD) level and the reverse signal XIN thereof is at the L (VSS) level, the n-type transistor N51 is ON, the n-type transistor N52 is OFF, the p-type transistor P51 is OFF, and the p-type transistor P52 is ON. One node W51 is at the L (VSS) level and the other node W52 is at the H (VDD3) level. In this steady state, since the n-type transistor N51 and the p-type transistor P51 are complementary to each other and the n-type transistor N52 and the p-type transistor P52 are complementary to each other, a current does not flow.
Thereafter, when the input signal IN is changed to the L (VSS) level and a state transition time starts, the n-type transistor N51 is turned OFF and the n-type transistor N52 is turned ON. Accordingly, a pass-through current flows from the high voltage supply VDD3 to the ground via the p-type transistor P52 and the n-type transistor N52 which are in an ON state, so that a potential of the node W52 starts dropping from the H (VDD3) level. When the potential of the node W52 drops to a level of VDD3-Vtp (Vtp is a threshold voltage of the p-type transistors P51 and P52) or less, the p-type transistor P51 starts to be turned ON and a potential of the node W51 (potential of the gate of the p-type transistor P52) is increased. Accordingly, a drain current in the p-type transistor P52 is reduced and the potential of the node W52 is further reduced.
Finally, the potential of the node W51 becomes the H (VDD3) level and the potential of the node W52 becomes the L (VSS) level. Accordingly, the pass-through current no longer flows therein, the output logic is reversed and a waiting state for a next input signal IN to be changed is started. In the description above, the case where the input signal IN is changed from the H level (VDD) to the L level (VSS) has been explained. The same operation also applies in a reversed case.
Another example of the level shift circuit is described, for example, in Patent Document 1.
(Patent Document 1) Japanese Patent No. 3477448
Assume that in the level shift circuit of FIG. 1, a current through each of the n-type transistors N51 and N52 at an ON operation is smaller than a current through each of the cross-coupled p-type transistors P51 and P52 at an ON operation. In this state, if the input signal IN is changed from “H” to “L”, the output signal OUT can not be made to be “L”. Therefore, the level shift circuit is not operated. Specifically, when the low voltage supply VDD is reduced to a low voltage, the driving ability of each of the n-type transistors N51 and N52 is reduced. Therefore, it becomes very difficult to ensure the operation of the level shift circuit at a low voltage.
To ensure a low voltage operation in such level shift circuit, for example, the following methods can be used.                I. An input voltage to the n-type transistors N51 and N52 is increased by an additional circuit such as a charge pump circuit.        II. Injection conditions and the like for the n-type transistors N51 and N52 are changed to reduce a threshold voltage.        III. The gate width size of the n-type transistors N51 and N52 is increased.        
First, in Method I, an input voltage to the n-type transistors N51 and N52 is increased by an additional circuit, thereby preventing reduction in driving current ability of the n-type transistors N51 and N52. Thus, the lower-limit operation voltage of the level shifter circuit can be lowered. However, providing the additional circuit disadvantageously causes increase in circuit area.
Next, in Method II, the driving current ability of the n-type transistors N51 and N52 can be increased by reducing the threshold voltage of the n-type transistors N51 and N52, so that the lower limit operation voltage of the level shift circuit can be reduced. However, injection conditions and the like have to be changed and process costs are disadvantageously increased.
Finally, in Method III, the driving current ability of the n-type transistors N51 and N52 can be increased by increasing the gate width size, so that the lower limit operation voltage of the level shift circuit can be reduced. However, increasing a transistor size disadvantageously causes increase in circuit area.
The above-described problems are not limited to the level shift circuit having the configuration of FIG. 1. Similar problems occur in a flip-flop type level shift circuit described in Patent Document 1 or some other level shift circuit (of a charge-pump type or a current mirror type) having a configuration in which a pair of complementary signals, i.e., an input signal and a reverse signal thereof are received at gates, respectively.